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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>LDAPURSB -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">LDAPURSB</h2>
      <p class="aml">Load-Acquire RCpc Register Signed Byte (unscaled) calculates an address from a base register and an immediate offset, loads a signed byte from memory, sign-extends it, and writes it to a register.</p>
      <p class="aml">The instruction has memory ordering semantics as described in <a class="armarm-xref" title="Reference to Armv8 ARM section">Load-Acquire, Load-AcquirePC, and Store-Release</a>, except that:</p>
      <ul>
        <li>There is no ordering requirement, separate from the requirements of a Load-AcquirePC or a Store-Release, created by having a Store-Release followed by a Load-AcquirePC instruction.</li>
        <li>The reading of a value written by a Store-Release by a Load-AcquirePC instruction by the same observer does not make the write of the Store-Release globally observed.</li>
      </ul>
      <p class="aml">This difference in memory ordering is not described in the pseudocode.</p>
      <p class="aml">For information about memory accesses, see <a class="armarm-xref" title="Reference to Armv8 ARM section">Load/Store addressing modes</a>.</p>
    
    <h3 class="classheading"><a id="iclass_base_plus_offset"/>Unscaled offset<span style="font-size:smaller;"><br/>(FEAT_LRCPC2)
          </span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td class="r">0</td><td class="l">0</td><td>1</td><td>1</td><td>0</td><td>0</td><td class="r">1</td><td class="l">1</td><td class="r">x</td><td class="lr">0</td><td colspan="9" class="lr">imm9</td><td class="l">0</td><td class="r">0</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rt</td></tr><tr class="secondrow"><td colspan="2" class="droppedname">size</td><td colspan="6"/><td colspan="2" class="droppedname">opc</td><td/><td colspan="9"/><td colspan="2"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">32-bit<span class="bitdiff"> (opc == 11)</span></h4><a id="LDAPURSB_32_ldapstl_unscaled"/><p class="asm-code">LDAPURSB  <a href="#sa_wt" title="32-bit general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Wt&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{, #<a href="#sa_simm" title="Optional signed immediate byte offset [-256-255], default 0 (field &quot;imm9&quot;)">&lt;simm&gt;</a>}]</p></div><div class="encoding"><h4 class="encoding">64-bit<span class="bitdiff"> (opc == 10)</span></h4><a id="LDAPURSB_64_ldapstl_unscaled"/><p class="asm-code">LDAPURSB  <a href="#sa_xt" title="64-bit general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Xt&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{, #<a href="#sa_simm" title="Optional signed immediate byte offset [-256-255], default 0 (field &quot;imm9&quot;)">&lt;simm&gt;</a>}]</p></div><p class="pseudocode">bits(64) offset = <a href="shared_pseudocode.html#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm9, 64);</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Wt&gt;</td><td><a id="sa_wt"/>
        
          <p class="aml">Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xt&gt;</td><td><a id="sa_xt"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xn|SP&gt;</td><td><a id="sa_xn_sp"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;simm&gt;</td><td><a id="sa_simm"/>
        
          <p class="aml">Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="postdecode"/><h3 class="pseudocode">Shared Decode</h3>
      <p class="pseudocode">integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer t = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rt);
<a href="shared_pseudocode.html#MemOp" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop;
boolean signed;
integer regsize;

if opc&lt;1&gt; == '0' then
    // store or zero-extending load
    memop = if opc&lt;0&gt; == '1' then <a href="shared_pseudocode.html#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> else <a href="shared_pseudocode.html#MemOp_STORE" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;
    regsize = 32;
    signed = FALSE;
else
    // sign-extending load
    memop = <a href="shared_pseudocode.html#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;
    regsize = if opc&lt;0&gt; == '1' then 32 else 64;
    signed = TRUE;

boolean tagchecked = memop != <a href="shared_pseudocode.html#MemOp_PREFETCH" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_PREFETCH</a> &amp;&amp; (n != 31);</p>
    </div>
  
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode">bits(64) address;
bits(8) data;

<a href="shared_pseudocode.html#AccessDescriptor" title="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc;
if memop == <a href="shared_pseudocode.html#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
    accdesc = <a href="shared_pseudocode.html#impl-shared.CreateAccDescLDAcqPC.1" title="function: AccessDescriptor CreateAccDescLDAcqPC(boolean tagchecked)">CreateAccDescLDAcqPC</a>(tagchecked);
elsif memop == <a href="shared_pseudocode.html#MemOp_STORE" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a> then
    accdesc = <a href="shared_pseudocode.html#impl-shared.CreateAccDescAcqRel.2" title="function: AccessDescriptor CreateAccDescAcqRel(MemOp memop, boolean tagchecked)">CreateAccDescAcqRel</a>(memop, tagchecked);

if n == 31 then
    if memop != <a href="shared_pseudocode.html#MemOp_PREFETCH" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_PREFETCH</a> then <a href="shared_pseudocode.html#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
    address = <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[];
else
    address = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

address = address + offset;

case memop of
    when <a href="shared_pseudocode.html#MemOp_STORE" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>
        data = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[t, 8];
        <a href="shared_pseudocode.html#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccessDescriptor accdesc] = bits(size*8) value_in">Mem</a>[address, 1, accdesc] = data;

    when <a href="shared_pseudocode.html#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>
        data = <a href="shared_pseudocode.html#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address, 1, accdesc];
        if signed then
            <a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[t, regsize] = <a href="shared_pseudocode.html#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(data, regsize);
        else
            <a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[t, regsize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(data, regsize);

    when <a href="shared_pseudocode.html#MemOp_PREFETCH" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_PREFETCH</a>
        <a href="shared_pseudocode.html#impl-aarch64.Prefetch.2" title="function: Prefetch(bits(64) address, bits(5) prfop)">Prefetch</a>(address, t&lt;4:0&gt;);</p>
    </div>
  <h3>Operational information</h3>
    <p class="aml">If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</p>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
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